Postdoctoral Modeling and mitigation approaches for device and wire reliability effects in deeply...
Many embedded applications not only exhibit throughput requirements but also the combination with hard latency constraints. That is the case in state-of-the-art wireless, multimedia and biomedical applications. Today's reliability modeling approaches cannot deal with time-efficient system-level analysis of complete platforms, and the mitigation approaches cannot meet these stringent reliability requirements for the large time-0 and time-dependent variations of the device and wire specifications in platforms fabricated with deeply scaled technology nodes. The only option available now is to restrict the analysis to a crude analyses (with pessimistic guard bands) and to accept a very large hardware (area and energy) cost, as in triple redundancy methods or guard-band based over dimensioning. That will needlessly increase the overhead and it will reduce the margin for further technology scaling.
Alternatively, we want to work on a time-efficient system-level analysis approaches which incorporate the full workload effect (no worst-case guard banding), and also on pure on-line mitigation techniques that are much more cost-effective because they are based on smart checkpointing and a heavily optimized run-time manager that takes care of hard throughput guarantees with minimal overhead of a few % in area and energy.
In this postdoc project we want to combine the existing knowledge of deep-submicron device and wire reliability models at IMEC with the use in advanced processor platforms running realistic application workloads. Our aim is to significantly increase the scaling potential of technologies with a large time-0 and time-dependent variability in the performance and energy figures-of-merit. We will also demonstrate this on realistic test cases. That will result in a large practical impact of the work in this postdoc.
This job comes from a partnership with Science Magazine and